 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| preliminary product specification ASD5020 high speed mode multi-mode 12-bit 640 msps / 8-bit 1000 msps analog to digital converter vestre rosten 81, 7075 tiller, norway org. no: no 991 265 163mva phone: +47 73 10 29 00, fax: +47 73 10 29 19 www.arcticsilicon.com page 1 of 34 description the ASD5020 is a versatile high performance low power analog-to-digital converter (adc), utilizing time-interleaving to increase sampling rate. integrated cross point switches activate the input selected by the user. in single channel mode, one of the four inputs can be selected as valid input to the single adc channel. in dual channel mode, any two of the four inputs can be selected to each adc channel. in quad channel mode, any input can be assigned to any adc channel. an internal, low jitter and programmable clock divider makes it possible to use a single clock source for all operational modes. the ASD5020 is based on a proprietary structure, and employs internal reference circuitry, a serial control interface and a serial lvds output data. data and frame synchronization clocks are supplied for data capture at the receiver. internal digital fine gain can be set separately for each adc to calibrate for gain errors. various modes and configuration settings can be applied to the adc through the serial control interface (spi). each channel can be powered down independently and output data format can be selected through this interface. a full chip idle mode can be set by a single external pin. register settings determine the exact function of this pin. ASD5020 is designed to interface easily with field programmable gate arrays (fpgas) from several vendors. features 12-bit modes single channel mode: f smax = 640 msps dual channel mode: f smax = 320 msps quad channel mode: f smax = 160 msps snr: 71 db, sfdr: 65 db 8-bit modes single channel mode: f smax = 1000 msps dual channel mode: f smax = 500 msps quad channel mode: f smax = 250 msps snr: 49 db, sfdr: 65 db integrated cross point switches with instantaneous switching internal low jitter programmable clock divider ultra low power dissipation 490mw including i/o at 640 msps 0.5 s start-up time from sleep, 15 s from power down internal reference circuitry with no external components required coarse and fine gain control digital fine gain adjustment for each adc internal offset correction 1.8 v supply voltage 1.7 - 3.6 v cmos logic on control interface pins serial lvds/rsds output 12, 14, 16 and dual 8-bit modes available 7mm x 7mm 48 qfn package applications precision oscilloscopes diversity receivers hi-end ultrasound communication testing non destructive testing figure 1 : functional block diagram lvds serial control interface c l k p c l k n s d a t a s c l k c s n d v d d a v s s a v d d fclkp fclkn lclkp lclkn p d r e s e t n d v s s ip1 in1 adc 1 digital gain lvds ip2 in2 adc 2 lvds ip4 in4 adc 4 lvds lvds adc 3 ip3 in3 digital gain digital gain digital gain c r o s s p o i n t s w i t c h e s ( m u x a r r a y ) dp1a dn1a dp1b dn1b dp2a dn2a dp2b dn2b dp3a dn3a dp3b dn3b dp4a dn4a dp4b dn4b pll clock divide 1/2/4/8 interleave
preliminary product specification table of contents blizzard product family: products and relations .................................................................................................................. 3 specifications ........................................................................................................................................................................ 4 ASD5020 high speed mode ........................................................................................................................................... 5 digital and switching specifications ...................................................................................................................................... 6 absolute maximum ratings .................................................................................................................................................. 7 pin configuration and description ......................................................................................................................................... 8 startup initialization ............................................................................................................................................................. 10 serial interface .................................................................................................................................................................... 10 timing diagram ............................................................................................................................................................. 10 timing diagrams ................................................................................................................................................................. 11 register map ....................................................................................................................................................................... 13 register description ........................................................................................................................................................... 15 software reset .............................................................................................................................................................. 15 modes of operation ...................................................................................................................................................... 15 input select .................................................................................................................................................................... 16 full-scale control .......................................................................................................................................................... 17 current control .............................................................................................................................................................. 17 start-up and clock jitter control ................................................................................................................................... 19 lvds output configuration and control ........................................................................................................................ 21 lvds drive strength programmability .......................................................................................................................... 24 lvds internal termination programmability .................................................................................................................. 24 power mode control ..................................................................................................................................................... 26 programmable gain ...................................................................................................................................................... 27 analog input invert ........................................................................................................................................................ 29 lvds test patterns ........................................................................................................................................................ 29 theory of operation ............................................................................................................................................................ 30 interleaving effects and sampling order ....................................................................................................................... 30 recommended usage ........................................................................................................................................................ 30 analog input .................................................................................................................................................................. 30 dc-coupling ............................................................................................................................................................ 31 ac-coupling ............................................................................................................................................................. 31 clock input and jitter considerations ............................................................................................................................ 31 application usage example ................................................................................................................................................ 32 start-up initialization ...................................................................................................................................................... 32 change mode ................................................................................................................................................................ 32 select analog input ........................................................................................................................................................ 32 package mechanical data .................................................................................................................................................. 33 qfn48 ........................................................................................................................................................................... 33 product information ............................................................................................................................................................. 34 ordering information ........................................................................................................................................................... 34 datasheet status ................................................................................................................................................................. 34 objective product specification: .................................................................................................................................... 34 preliminary product specification: ................................................................................................................................. 34 product specification: .................................................................................................................................................... 34 life support applications : ....................................................................................................................................... 34 ASD5020 rev 2.0 , 2010.11.08 high speed mode page 2 of 34 preliminary product specification blizzard product family: products and relations ASD5020 is a part of the asd blizzard family of adcs for instrumentation applications, with two main modes: ? high speed mode (ASD5020hs): 12-bit up to 640msps ? precision mode (ASD5020pm): 14-bit up to 105msps the blizzard family also includes asd5010 with 8-bit up to 1gsps blizzard adcs are pin compatible. the products within the family can be configured with the spi interface. the ASD5020 modes can be chosen by spi configuration. additionally, ASD5020 can be configured as asd5010. asd5010 can not be configured as ASD5020. this relationship is shown in figure 2 ASD5020 rev 2.0 , 2010.11.08 high speed mode page 3 of 34 figure 2 : blizzard product family ASD5020 high speed mode (ASD5020hs) single/dual/quad 12-bit 640/320/160 msps adc asd5010 single/dual/quad 8-bit 1000/500/250 msps adc spi spi spi ASD5020 precision mode (ASD5020pm) quad 14-bit 105 msps adc preliminary product specification specifications avdd=dvdd=ovdd=1.8v, f s = 160 msps, quad channel 12-bit high speed mode, 50% clock duty cycle, -1dbfs 70 mhz input signal, 1x/0db digital gain (fine and coarse), unless otherwise noted parameter description min typ max unit dc accuracy no missing codes guaranteed off set offset error after internal digital offset correction 1 lsb g abs gain error 6 %fs g rel gain matching between channels. 3sigma value at worst case conditions 0.5 %fs dnl differential non linearity 0.2 lsb inl integral non linearity 0.6 lsb v cm,out common mode voltage output v avdd /2 analog input v cm,in analog input common mode voltage v cm -0.1 v cm +0.2 v fsr differential input voltage full scale range 2.0 vpp c in,q differential input capacitance, quad channel mode 5 pf c in,d differential input capacitance, dual channel mode 7 pf c in,s differential input capacitance, single channel mode 11 pf fpbw full power bandwidth 700 mhz f inmax_2vpp maximum input frequency @ 2vpp full scale range 500 mhz f inmax_1vpp maximum input frequency @ 1vpp full scale range 800 mhz power supply v avdd analog supply voltage 1.7 1.8 2.0 v v dvdd digital and output driver supply voltage 1.7 1.8 2.0 v v ovdd digital cmos input supply voltage 1.7 1.8 3.6 v temperature t a operating free-air temperature -40 85 c ASD5020 rev 2.0 , 2010.11.08 high speed mode page 4 of 34 preliminary product specification ASD5020 high speed mode avdd=dvdd=ovdd=1.8v, 50% clock duty cycle, -1dbfs 70 mhz input signal, gain = 1x, 12-bit output, rsds output data levels, unless otherwise noted parameter description min typ max unit performance snr signal to noise ratio single channel mode , f s = 640 msps 70 dbfs single channel mode , f s = 640 msps gain = 10x 52 dbfs dual channel mode , f s = 320 msps 70 dbfs quad channel mode , f s = 160 msps 70 dbfs sinad signal to noise and distortion ratio single channel mode , f s = 640 msps 62 dbfs single channel mode , f s = 640 msps, gain = 10x 51 dbfs dual channel mode , f s = 320 msps 66 dbfs quad channel mode , f s = 160 msps 67 dbfs sfdr spurious free dynamic range single channel mode , f s = 640 msps 65 dbc dual channel mode , f s = 320 msps 65 dbc quad channel mode , f s = 160 msps 65 dbc enob effective number of bits single channel mode , f s = 640 msps 10.0 bits single channel mode , f s = 640 msps, gain = 10x 8.0 bits dual channel mode , f s = 320 msps 10.6 bits quad channel mode , f s = 160 msps 10.8 bits x tlk,hs2 crosstalk dual ch mode. signal applied to 1 channel (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 = 8 mhz, f in0 = 9.9 mhz tbd dbc x tlk,hs4 crosstalk quad ch mode. signal applied to 1 channel (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 = 8 mhz, f in0 = 9.9 mhz tbd dbc power supply single ch: f s = 640 msps, dual ch: f s = 320 msps, quad ch: f s = 160 msps. i avdd analog supply current 190 ma i dvdd digital and output driver supply current 82 ma p avdd analog power 342 mw p dvdd digital power 148 mw p tot total power dissipation 490 mw p pd power down mode dissipation 15 w p slp deep sleep mode power dissipation 66 mw p slpch power dissipation with all channels in sleep channel mode (light sleep) 121 mw p slpch_sav power dissipation savings per channel off 92 mw clock inputs f smax max. conversion rate in modes: single / dual / quad channel 640 / 320 / 160 msps f smin min. conversion rate in modes: single / dual / quad channel 120 / 60 / 30 msps ASD5020 rev 2.0 , 2010.11.08 high speed mode page 5 of 34 preliminary product specification digital and switching specifications avdd= dvdd=ovdd=1.8v, rsds output data levels, unless otherwise noted parameter description min typ max unit clock inputs dc duty cycle 40 60 % high compliance cmos, lvds, lvpecl v ck,diff differential input voltage swing +/-200 mvpp v ck,sine differential input voltage swing, sine wave clock input +/-800 mvpp v ck,cmos voltage input range cmos (clkn connected to ground) v ovdd v cm,ck input common mode voltage. keep voltages within ground and voltage of ovdd 0.3 v ovdd -0.3 v c ck differential input capacitance 3 pf logic inputs (cmos) v hi high level input voltage. v ovdd 3.0v 2 v v hi high level input voltage. v ovdd = 1.7v C 3.0v 0.8 v ovdd v v li low level input voltage. v ovdd 3.0v 0 0.8 v v li low level input voltage. v ovdd = 1.7v C 3.0v 0 0.2 v ovdd v i hi high level input leakage current +/-10 a i li low level input leakage current +/-10 a c i input capacitance 3 pf data outputs compliance lvds / rsds v out differential output voltage, lvds 350 mv v out differential output voltage, rsds 150 mv v cm output common mode voltage 1.2 v output coding default/optional offset binary/ 2's complement timing characteristics t a aperture delay 1.5 ns t j aperture jitter, all bits set to '1' in jitter_ctrl<7:0> 120 fsrms t j aperture jitter, one bit set to '1' in jitter_ctrl<7:0> 160 fsrms t skew timing skew between adc channels 2.5 psrms t su start up time from power down mode and deep sleep mode to active mode in s. see section "clock frequency" for details. 15 s t slpch start up time from sleep channel mode to active mode 0.5 s t ovr out of range recovery time 1 clock cycles t lathsmq pipeline delay, quad high speed mode 32 clock cycles t lathsmd pipeline delay, dual high speed mode 64 clock cycles t lathsms pipeline delay, single high speed mode 128 clock cycles lvds output timing characteristics t data lclk to data delay time (excluding programmable phase shift) 50 ps t prop clock propagation delay. 6*t lvds +2.2 7*t lvds +3.5 7*t lvds +5.0 ns lvds bit-clock duty-cycle 45 55 % lclk cycle frame clock cycle-to-cycle jitter 2.5 % lclk cycle t edge data rise- and fall time 20% to 80% 0.7 ns t clkedge clock rise- and fall time 20% to 80% 0.7 ns ASD5020 rev 2.0 , 2010.11.08 high speed mode page 6 of 34 preliminary product specification absolute maximum ratings applying voltages to the pins beyond those specified in table 1 could cause permanent damage to the circuit. table 1 : maximum voltage ratings pin reference pin rating avdd avss -0.3v to +2.3v dvdd dvss -0.3v to +2.3v ovdd avss -0.3v to +3.9v avss / dvss dvss / avss -0.3v to +0.3v analog inputs and outputs avss -0.3v to +2.3v clkx avss -0.3v to +3.9v lvds outputs dvss -0.3v to +2.3v digital inputs dvss -0.3v to +3.9v table 2 shows the maximum external temperature ratings. table 2 : maximum temperature ratings operating temperature -40 to +85 o c storage temperature -60 to +150 o c soldering profile qualification j-std-020 this device can be damaged by esd. even though this product is protected with state-of-the-art esd protection circuitry, damage may occur if the device is not handled with appropriate precautions. esd damage may range from device failure to performance degradation. analog circuitry may be more susceptible to damage as vary small parametric changes can result in specification noncompliance. ASD5020 rev 2.0 , 2010.11.08 high speed mode page 7 of 34 preliminary product specification pin configuration and description table 3 : pin descriptions pin name description pin number # of pins avdd analog power supply, 1.8v 1, 36 2 csn chip select enable. active low 2 1 sdata serial data input 3 1 sclk serial clock input 4 1 resetn reset spi interface. active low 5 1 pd power-down input. activate after applying power in order to initialize the adc correctly. alternatively use the spi power down feature 6 1 dvdd digital and i/o power supply, 1.8v 7, 30 2 dvss digital ground 8, 29 2 dp1a lvds channel 1a, positive output 9 1 dn1a lvds channel 1a, negative output 10 1 dp1b lvds channel 1b, positive output 11 1 dn1b lvds channel 1b, negative output 12 1 dp2a lvds channel 2a, positive output 13 1 dn2a lvds channel 2a, negative output 14 1 ASD5020 rev 2.0 , 2010.11.08 high speed mode page 8 of 34 1 2 3 4 5 6 7 9 10 11 12 8 36 ovdd 35 clkp 34 clkn 33 avdd2 32 avss2 30 dvdd 29 dvss 28 dn4b 27 dp4b 31 avdd 26 dn4a 25 dp4a d p 2 a d n 2 a d p 2 b d n 2 b l c l k p l c l k n f c l k p f c l k n d p 3 a d n 3 a d p 3 b d n 3 b 3 7 i n 4 3 8 i p 4 3 9 a v s s 4 0 i n 3 4 1 i p 3 4 2 a v s s 4 3 i n 2 4 4 i p 2 4 5 a v s s 4 6 i n 1 4 7 i p 1 4 8 v c m 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 avdd csn sdata sclk resetn dvdd dvss dp1a dn1a pd dp1b dn1b figure 3 : package diagram preliminary product specification pin name description pin number # of pins dp2b lvds channel 2b, positive output 15 1 dn2b lvds channel 2b, negative output 16 1 lckp lvds bit clock, positive output 17 1 lckn lvds bit clock, negative output 18 1 fclkp lvds frame clock (1x), positive output 19 1 fclkn lvds frame clock (1x), negative output 20 1 dp3a lvds channel 3a, positive output 21 1 dn3a lvds channel 3a, negative output 22 1 dp3b lvds channel 3b, positive output 23 1 dn3b lvds channel 3b, negative output 24 1 dp4a lvds channel 4a, positive output 25 1 dn4a lvds channel 4a, negative output 26 1 dp4b lvds channel 4b, positive output 27 1 dn4b lvds channel 4b, negative output 28 1 avss2 analog ground domain 2 31 1 avdd2 analog power supply domain 2, 1.8v 32 1 ovdd digital cmos inputs supply voltage 33 1 clkn negative differential input clock. 34 1 clkp positive differential input clock 35 1 in4 negative differential input signal, channel 4 37 1 ip4 positive differential input signal, channel 4 38 1 avss analog ground 39, 42, 45 3 in3 negative differential input signal, channel 3 40 1 ip3 positive differential input signal, channel 3 41 1 in2 negative differential input signal, channel 2 43 1 ip2 positive differential input signal, channel 2 44 1 in1 negative differential input signal, channel 1 46 1 ip1 positive differential input signal, channel 1 47 1 vcm common mode output pin, 0.5*avdd 48 1 ASD5020 rev 2.0 , 2010.11.08 high speed mode page 9 of 34 preliminary product specification startup initialization as part of the ASD5020 power-on sequence both a reset and a power down cycle have to be applied to ensure correct start-up initialization. reset can be done in one of two ways: 1. b y applying a low-going pulse (minimum 20 ns) on the resetn pin (asynchronous). 2. by using the serial interface to set the 'rst' bit high. internal registers are reset to default values when this bit is set. the 'rst' bit is self-reset to zero. when using this method, do not apply any low-going pulse on the resetn pin. power down cycling can be done in one of two ways: 1. by applying a high-going pulse (minimum 20 ns) on the pd pin (asynchronous). 2. by cycling the 'pd' bit in register 0f hex to high (reg value '0200' hex ) and then low (reg value '0000' hex ). serial interface the ASD5020 configuration registers can be accessed through a serial interface formed by the pins sdata (serial interface data), sclk (serial interface clock) and csn (chip select, active low). the following occurs when csn is set low: serial data are shifted into the chip at every rising edge of sclk, the value present at sdata is latched sdata is loaded into the register every 24th rising edge of sclk multiples of 24-bit words data can be loaded within a single active csn pulse. if more than 24 bits are loaded into sdata during one active csn pulse, only the first 24 bits are kept. the excess bits are ignored. every 24-bit word is divided into two parts: the first eight bits form the register address the remaining 16 bits form the register data acceptable sclk frequencies are from 20mhz down to a few hertz. duty-cycle does not have to be tightly controlled. timing diagram figure 4 shows the timing of the serial port interface. table 4 explains the timing variables used in figure 4 . table 4 : serial port interface timing definitions parameter description minimum value unit t cs setup time between csn and sclk 8 ns t ch hold time between csn and sclk 8 ns t hi sclk high time 20 ns t lo sclk low time 20 ns t ck sclk period 50 ns t s data setup time 5 ns t h data hold time 5 ns ASD5020 rev 2.0 , 2010.11.08 high speed mode page 10 of 34 figure 4 : serial port interface timing csn sclk sdata t s t h t cs t chi t hi t lo t ck t ch a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 preliminary product specification timing diagrams figure 5 : quad channel - lvds timing 12-bit output figure 6 : dual channel - lvds timing 12-bit output ASD5020 rev 2.0 , 2010.11.08 high speed mode page 11 of 34 t lvds d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n n n n n n n n n n n n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 analog input input clock lclk p lclk n fclk n fclk p dxna n-4 n-4 d10 d11 t prop d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 dxnb n-3 n-3 d10 d11 n+32 n+34 n+33 n+31 n+35 t lvds d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n n n n n n n n n n n n-4 n-4 n-4 n-4 n-4 n-4 n-4 n-4 n-4 n-4 n-4 n-4 analog input input clock lclk p lclk n fclk n fclk p n-8 n-8 d10 d11 t prop d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n-3 n-3 n-3 n-3 n-3 n-3 n-3 n-3 n-3 n-3 n-3 n-3 n-7 n-7 d10 d11 n+64 n+68 n+66 n+62 n+70 n+69 n+67 n+65 n+63 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-6 n-6 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n+3 n+3 n+3 n+3 n+3 n+3 n+3 n+3 n+3 n+3 n+3 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-5 n-5 d10 d11 n+2 n+2 n+2 n+2 n+2 n+2 n+2 n+2 n+2 n+2 n+2 dx1a / dx3a dx1b / dx3b dx2a / dx4a dx2b / dx4b preliminary product specification figure 7 : single channel - lvds timing 12-bit output figure 8 : lvds data timing ASD5020 rev 2.0 , 2010.11.08 high speed mode page 12 of 34 t lvds t lvds /2 dxxx t data lclk p lclk n t lvds d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n n n n n n n n n n n n-8 n-8 n-8 n-8 n-8 n-8 n-8 n-8 n-8 n-8 n-8 n-8 analog input input clock lclk p lclk n fclk n fclk p d10 d11 t prop d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n-7 n-7 n-7 n-7 n-7 n-7 n-7 n-7 n-7 n-7 n-7 n-7 d10 d11 n+128 n+136 n+132 n+124 n+140 n+138 n+134 n+130 n+126 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n-6 n-6 n-6 n-6 n-6 n-6 n-6 n-6 n-6 n-6 n-6 n-6 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n+3 n+3 n+3 n+3 n+3 n+3 n+3 n+3 n+3 n+3 n+3 n-5 n-5 n-5 n-5 n-5 n-5 n-5 n-5 n-5 n-5 n-5 n-5 d10 d11 n+2 n+2 n+2 n+2 n+2 n+2 n+2 n+2 n+2 n+2 n+2 dx1a dx1b dx2a dx2b d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n-4 n-4 n-4 n-4 n-4 n-4 n-4 n-4 n-4 n-4 n-4 n-4 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n+5 n+5 n+5 n+5 n+5 n+5 n+5 n+5 n+5 n+5 n+5 n-3 n-3 n-3 n-3 n-3 n-3 n-3 n-3 n-3 n-3 n-3 n-3 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-10 n-10 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n+7 n+7 n+7 n+7 n+7 n+7 n+7 n+7 n+7 n+7 n+7 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-9 n-9 d10 d11 n+6 n+6 n+6 n+6 n+6 n+6 n+6 n+6 n+6 n+6 n+6 dx3a dx3b dx4a dx4b n+4 n+4 n+4 n+4 n+4 n+4 n+4 n+4 n+4 n+4 n+4 n-11 n-11 n-12 n-12 n-13 n-13 n-14 n-14 n-15 n-15 n-16 n-16 preliminary product specification register map table 5 : register map - ASD5020 name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address rst * self-clearing software reset. inactive x 0x00 sleep4_ch<4:1> channel-specific sleep mode for a quad channel setup. inactive x x x x 0x0f sleep2_ch<2:1> channel-specific sleep mode for a dual channel setup. inactive x x sleep1_ch1 channel-specific sleep mode for a single channel setup. inactive x sleep go to sleep-mode. inactive x pd go to power-down. inactive x pd_pin_cfg<1:0> configures the pd pin function. pd pin configured for power-down mode x x ilvds_lclk<2:0> lvds current drive programmability for lclkp and lclkn pins. 3.5 ma drive x x x 0x11 ilvds_frame<2:0> lvds current drive programmability for fclkp and fclkn pins. 3.5 ma drive x x x ilvds_dat<2:0> lvds current drive programmability for output data pins. 3.5 ma drive x x x en_lvds_term enables internal termination for lvds buffers. termination disabled x 0x12 term_lclk<2:0> programmable termination for lclkn and lclkp buffers. termination disabled 1 x x x term_frame<2:0> programmable termination for fclkn and fclkp buffers. termination disabled 1 x x x term_dat<2:0> programmable termination for output data buffers. termination disabled 1 x x x invert4_ch<4:1> channel specific swapping of the analog input signal for a quad channel setup. ipx is positive input x x x x 0x24 invert2_ch<2:1> channel specific swapping of the analog input signal for a dual channel setup. ipx is positive input x x invert1_ch1 channel specific swapping of the analog input signal for a single channel setup. ipx is positive input x en_ramp enables a repeating full-scale ramp pattern on the outputs. inactive x 0 0 0x25 dual_custom_pat enable the mode wherein the output toggles between two defined codes. inactive 0 x 0 single_custom_pat enables the mode wherein the output is a constant specified code. inactive 0 0 x bits_custom1 <15:0> bits for the single custom pattern and for the first code of the dual custom pattern. <0> is the lsb. 0x0000 x x x x x x x x x x x x x x x x 0x26 bits_custom2 <15:0> bits for the second code of the dual custom pattern. 0x0000 x x x x x x x x x x x x x x x x 0x27 cgain4_ch1 <3:0> programmable coarse gain channel 1 in a quad channel setup. 1x gain x x x x 0x2a cgain4_ch2 <3:0> programmable coarse gain channel 2 in a quad channel setup. 1x gain x x x x cgain4_ch3 <3:0> programmable coarse gain channel 3 in a quad channel setup. 1x gain x x x x cgain4_ch4 <3:0> programmable coarse gain channel 4 in a quad channel setup. 1x gain x x x x cgain2_ch1 <3:0> programmable coarse gain channel 1 in a dual channel setup. 1x gain x x x x 0x2b cgain2_ch2 <3:0> programmable coarse gain channel 2 1x gain x x x x ASD5020 rev 2.0 , 2010.11.08 high speed mode page 13 of 34 preliminary product specification name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address in a dual channel setup. cgain1_ch1 <3:0> programmable coarse gain channel 1 in a single channel setup. 1x gain x x x x jitter_ctrl<7:0> clock jitter adjustment. 160 fsrms x x x x x x x x 0x30 precision_mode * enable quad channel 14 bits precision mode. inactive x 0x31 high_speed_mode * <2:0> enable high speed mode, single, dual or quad channel. high speed mode C quad channel x x x clk_divide<1:0> * define clock divider factor: 1, 2, 4 or 8 divide by 1 x x coarse_gain_cfg configures the coarse gain setting x-gain enabled x 0x33 fine_gain_en enable use of fine gain. disabled x fgain_branch1<6:0> programmable fine gain for branch1. 1x / 0db gain x x x x x x x 0x34 fgain_branch2<6:0> programmable fine gain for branch 2. 1x / 0db gain x x x x x x x fgain_branch3<6:0> programmable fine gain for branch 3. 1x / 0db gain x x x x x x x 0x35 fgain_branch4<6:0> programmable fine gain for branch 4. 1x / 0db gain x x x x x x x fgain_branch5<6:0> programmable fine gain for branch 5. 1x / 0db gain x x x x x x x 0x36 fgain_branch6<6:0> programmable fine gain for branch 6. 1x / 0db gain x x x x x x x fgain_branch7<6:0> programmable fine gain for branch 7. 1x / 0db gain x x x x x x x 0x37 fgain_branch8<6:0> programmable fine gain for branch 8. 1x / 0db gain x x x x x x x inp_sel_adc1<4:0> input select for adc 1. signal input: ip1/in1 x x x x x 0x3a inp_sel_adc2<4:0> input select for adc 2. signal input: ip2/in2 x x x x x inp_sel_adc3<4:0> input select for adc 3. signal input: ip3/in3 x x x x x 0x3b inp_sel_adc4<4:0> input select for adc 4. signal input: ip4/in4 x x x x x phase_ddr<1:0> controls the phase of the lclk output relative to data. 90 degrees x x 0x42 pat_deskew enable deskew pattern mode. inactive 0 x 0x45 pat_sync enable sync pattern mode. inactive x 0 btc_mode binary two's complement format for adc output data. straight offset binary x 0x46 msb_first serialized adc output data comes out with msb first. lsb first x adc_curr<2:0> adc current scaling. nominal x x x 0x50 ext_vcm_bc<1:0> vcm buffer driving strength control. nominal x x lvds_pd_mode controls lvds power down mode high z-mode x 0x52 lvds_output_mode <2:0> * sets the number of lvds output bits. 12 bit x x x 0x53 low_clk_freq * low clock frequency used. inactive x lvds_advance advance lvds data bits and frame clock by one clock cycle inactive 0 x lvds_delay delay lvds data bits and frame clock by one clock cycle inactive x 0 fs_cntrl<5:0> fine adjust adc full scale range 0% change x x x x x x 0x55 startup_ctrl<2:0> * controls start-up time. '000' x x x 0x56 undefined register addresses must not be written to; incorrect behavior may be the result. unused register bits (blank table cells) must be set to '0' when programming the registers. all registers can be written to while the chip is in power down. *) these registers requires a power down cycle when written to (see startup initialization ). ASD5020 rev 2.0 , 2010.11.08 high speed mode page 14 of 34 preliminary product specification register description software reset name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address rst self-clearing software reset. inactive x 0x00 setting the rst register bit to '1', restores the default value of all the internal registers including the rst register bit itself. modes of operation name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address high_speed_mode <2:0> enable high speed mode, single, dual or quad channel. high speed mode C quad channel 0 x x x clk_divide<1:0> define clock divider factor: 1, 2, 4 or 8 divide by 1 x x the ASD5020 has three main high speed operating modes controlled by the register bit high_speed_mode as defined in table 6 . power down mode, as described in section 'startup initialization', must be activated after or during a change of operating mode to ensure correct operation. the high speed modes all utilize interleaving to achieve high sampling speed. quad channel mode interleaves 2 adc branches, dual channel mode interleaves 4 adc branches, while single channel mode interleave all 8 adc branches. table 6 : modes of operation high_speed_mode <2:0> mode of operation description 0 0 1 single channel 12-bit high speed mode single channel by interleaving adc1to adc4 0 1 0 dual channel 12-bit high speed mode dual channel where channel 1 is made by interleaving adc1 and adc2, channel 2 by interleaving adc3 and adc4 1 0 0 quad channel 12-bit high speed mode quad channel where channel 1 corresponds to adc1, channel2 to adc2, channel3 to adc3 and channel 4 to adc4 only one of the 3 bits should be activated at the same time. clk_divide<1:0> allows the user to apply an input clock frequency higher than the sampling rate. the clock divider will divide the input clock frequency by a factor of 1, 2, 4, or 8, defined by the clk_divide<1:0> register. by setting the clk_divide<1:0> value relative to the channel_num<2:0> value, the same input clock frequency can be used for all settings on number of channels. e.g: when increasing the number of channels from 1 to 4, the maximum sampling rate is reduced by a factor of 4. by letting clk_divide<1:0> follow the channel_num<2:0> value, and change it from 1 to 4, the internal clock divider will provide the reduction of the sampling rate without changing the input clock frequency. table 7 : clock divider factor clk_divide<1:0> clock divider factor sampling rate (fs) 00 (default) 1 input clock frequency / 1 01 2 input clock frequency / 2 10 4 input clock frequency / 4 11 8 input clock frequency / 8 ASD5020 rev 2.0 , 2010.11.08 high speed mode page 15 of 34 preliminary product specification input select name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address inp_sel_adc1<4:0> input select for adc 1. signal input: ip1/in1 x x x x 0 0x3a inp_sel_adc2<4:0> input select for adc 2. signal input: ip2/in2 x x x x 0 inp_sel_adc3<4:0> input select for adc 3. signal input: ip3/in3 x x x x 0 0x3b inp_sel_adc4<4:0> input select for adc 4. signal input: ip4/in4 x x x x 0 each adc is connected to the four input signals via a full flexible cross point switch, set up by inp_sel_adcx . in single channel mode, any one of the four inputs can be selected as valid input to the single adc channel. in dual channel mode, any two of the four inputs can be selected to each adc channel. in quad channel mode, any input can be assigned to any adc channel. the switching of inputs can be done during normal operation, and no additional actions are needed. the switching will occur instantaneously at the end of each spi command. table 8 : adc input select inp_sel_adcx<4:0> selected input 0001 0 ip1/in1 0010 0 ip2/in2 0100 0 ip3/in3 1000 0 ip4/in4 other do not use figure 9 : adc input signals through cross point switch ASD5020 rev 2.0 , 2010.11.08 high speed mode page 16 of 34 cross point switch (analog mux) adc 1 <4:1> ip1 / in1 inp_sel_adc1<4:1> adc 2 <4:1> ip2 / in2 inp_sel_adc2<4:1> adc 3 <4:1> ip3 / in3 inp_sel_adc3<4:1> adc 4 <4:1> ip4 / in4 inp_sel_adc4<4:1> preliminary product specification full-scale control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address fs_cntrl<5:0> fine adjust adc full scale range 0% change x x x x x x 0x55 the full-scale voltage range of ASD5020 can be adjusted using an internal 6-bit dac controlled by the fs_cntrl register. changing the value in the register by one step, adjusts the full-scale range by approximately 0.3%. this leads to a maximum range of 10% adjustment. table 9 shows how the register settings correspond to the full-scale range. note that the values for full-scale range adjustment are approximate. the dac is, however, guaranteed to be monotonous. the full-scale control and the programmable gain features differ in two major ways: 1. the full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable gain is a digital feature. 2. the programmable gain feature has much coarser gain steps and larger range than the full-scale control. table 9 : register values with corresponding change in full-scale range fs_cntrl<5:0> full-scale range adjustment 111111 +9.7% 111110 +9.4% ... ... 100001 +0.3% 100000 +0% 011111 ?0.3% ... ... 000001 ?9.7% 000000 ?10% current control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address adc_curr<2:0> adc current scaling. nominal x x x 0x50 ext_vcm_bc<1:0> vcm buffer driving strength control. nominal x x there are two registers that impact performance and power dissipation. the adc_curr register scales the current consumption in the adc core. the performance is guaranteed at the nominal setting. lower power consumption can be achieved by reducing the adc_curr value, see table 10 . the impact on performance will depend on the adc sampling rate. table 10 : adc current control settings adc_curr<2:0> adc core current 100 -40% 101 -30% 110 -20% 111 -10% 000 (default) nominal 001 do not use 010 do not use 011 do not use ASD5020 rev 2.0 , 2010.11.08 high speed mode page 17 of 34 preliminary product specification the ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the vcm pin. if this pin is not in use, the buffer can be switched off. if current is drawn from the vcm pin, the driving strength can be increased to keep the voltage on this pin at the correct level. table 11 : external common mode voltage buffer driving strength ext_vcm_bc<1:0> vcm buffer driving strength [a] max current sinked/sourced from vcm pin with < 20 mv voltage change. 00 off (vcm floating) 01 (default) +/-20 10 +/-400 11 +/-700 ASD5020 rev 2.0 , 2010.11.08 high speed mode page 18 of 34 preliminary product specification start-up and clock jitter control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address startup_ctrl<2:0> controls start-up time. '000' x x x 0x56 jitter_ctrl<7:0> clock jitter adjustment. 160 fsrms x x x x x x x x 0x30 to optimize start up time, a register is provided where the start-up time in number of clock cycles can be set. some internal circuitry have start up times that are clock frequency independent. default counter values are set to accommodate these start up times at the maximum clock frequency (sampling rate). this will lead to increased start up times at low clock frequencies. setting the value of this register to the nearest higher clock frequency will reduce the count values of the internal counters, to better fit the actual start up time, such that the start up time will be reduced. the start up times from power down and sleep modes are changed by this register setting. if the clock divider is used (set to other than 1), the input clock frequency must be divided by the divider factor to find the correct clock frequency range (see table 7 ). table 12 : start-up time control settings quad channel dual channel startup_ ctrl<2:0> clock frequency range [msps] startup delay [clock cycles] startup delay [s] startup_ ctrl<2:0> clock frequency range [msps] startup delay [clock cycles] startup delay [s] 100 160 - 250 3072 12.3 C 19.2 100 320 - 500 6144 12.3 C 19.2 000 100 - 160 1984 12.4 - 19.8 000 200 - 320 3968 12.4 - 19.8 001 65 - 100 1280 12.8 - 19.7 001 130 C 200 2560 12.8 - 19.7 010 40 - 65 840 12.9 - 21 010 80 - 130 1680 12.9 - 21 011 30 - 40 520 13 - 17.3 011 60 C 80 1040 13 - 17.3 other do not use - - other do not use - - single channel startup_ ctrl<2:0> clock frequency range [msps] startup delay [clock cycles] startup delay [s] 100 640 - 1000 12288 12.3 C 19.2 000 400 - 640 7936 12.4 - 19.8 001 260 - 400 5120 12.8 - 19.7 010 160 - 260 3360 12.9 - 21 011 120 - 160 2080 13 - 17.3 other do not use - - ASD5020 rev 2.0 , 2010.11.08 high speed mode page 19 of 34 preliminary product specification jitter_ctrl<7:0> allows the user to set a trade-off between power consumption and clock jitter. if all bits in the register is set low, the clock signal is stopped. the clock jitter depends on the number of bits set to '1' in the jitter_ctrl<7:0> register. which bits are set high does not affect the result. table 13 : clock jitter performance number of bits to '1' in jitter_ctrl<7:0> clock jitter performance high speed mode [fsrms] module current consumption [ma] 1 160 1 2 150 2 3 136 3 4 130 4 5 126 5 6 124 6 7 122 7 8 120 8 0 clock stopped ASD5020 rev 2.0 , 2010.11.08 high speed mode page 20 of 34 preliminary product specification lvds output configuration and control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address lvds_output_mode <2:0> sets the number of lvds output bits. 12 bit x x x 0x53 low_clk_freq low clock frequency used. inactive x lvds_advance advance lvds data bits and frame clock by one clock cycle inactive 0 x lvds_delay delay lvds data bits and frame clock by one clock cycle inactive x 0 phase_ddr<1:0> controls the phase of the lclk output relative to data. 90 degrees x x 0x42 btc_mode binary two's complement format for adc output data. straight offset binary x 0x46 msb_first serialized adc output data comes out with msb first. lsb first x the ASD5020 serial lvds output has four different modes selected by the register lvds_output_mode as defined in table 14 . power down mode, as described in section 'startup initialization', must be activated after or during a change in the number of output bits to ensure correct behavior. table 14 : number of bits in lvds output lvds_output_mode<2:0> number of bits comment 000 8 bit 8 bit mode, up to 1gsps (asd5010) 001 12 bit default setting for high speed modes 010 14 bit 011 16 bit other do not use for the high speed modes only the 12, 14 and 16-bit lvds output modes are available. when 14 or 16 bit lvds output mode is selected the output data will be a 13 bit left justified word filled up with '0's on the lsb side. the different high speed modes uses the lvds outputs as defined by table 15 . table 15 : high speed modes and use of lvds outputs high speed modes/ channels lvds outputs used single channel d1a, d1b, d2a, d2b, d3a, d3b, d4a, d4b dual channel, channel 1 d1a, d1b, d2a, d2b dual channel, channel 2 d3a, d3b, d4a, d4b quad channel, channel 1 d1a, d1b quad channel, channel 2 d2a, d2b quad channel, channel 3 d3a, d3b quad channel, channel 4 d4a, d4b maximum data output bit-rate for the ASD5020 is 1 gb/s. the maximum sampling rate for the different configurations is given by table 16 . the sampling rate is set by the frequency of the input clock (f s ). the frame-rate, i.e. the frequency of the fclk signal on the lvds outputs, depends on the selected mode and the sampling frequency (f s ) as defined in table 17 . ASD5020 rev 2.0 , 2010.11.08 high speed mode page 21 of 34 preliminary product specification table 16 : maximum sampling rate vs number of output bits for different ASD5020 configurations number of bits single channel high speed [msps] dual channel high speed [msps] quad channel high speed [msps] 12 660 330 165 14 560 280 140 16 500 250 125 dual 8 - - - table 17 : output data frame rate mode of operation frame-rate (fclk frequency) high speed, single channel f s / 8 high speed, dual channel f s / 4 high speed, quad channel f s / 2 if the ASD5020 device is used at a low sampling rate the register bit low_clk_freq has to be set to '1'. see table 18 for when to use this register bit for the different modes of operation. table 18 : use of register bit low_clk_freq mode of operation limit when low_clk_freq should be activated high speed, single channel f s < 240 mhz high speed, dual channel f s < 120 mhz high speed, quad channel f s < 60 mhz ASD5020 rev 2.0 , 2010.11.08 high speed mode page 22 of 34 preliminary product specification to ease timing in the receiver when using multiple ASD5020 , the device has the option to adjust the timing of the output data and the frame clock. the propagation delay with respect to the adc input clock can be moved one lvds clock cycle forward or backward, by using lvds_delay and lvds_advance , respectively. see figure 10 for details. note that lclk is not affected by lvds_delay or lvds_advance settings. the lvds output interface of ASD5020 is a ddr interface. the default setting is with the lclk rising and falling edge transitions in the middle of alternate data windows. the phase for lclk can be programmed relative to the output frame clock and data bits using phase_ddr<1:0> . the lclk phase modes are shown in figure 11 . the default timing is identical to setting phase_ddr<1:0> ='10'. figure 11 : phase programmability modes for lclk the default data output format is offset binary. two's complement mode can be selected by setting the btc_mode bit to '1' which inverts the msb. the first bit of the frame (following the rising edge of fclkp) is the lsb of the adc output for default settings. programming the msb_first mode results in reverse bit order, and the msb is output as the first bit following the fclkp rising edge. ASD5020 rev 2.0 , 2010.11.08 high speed mode page 23 of 34 fclk n fclk p lclk p lclk n dxx<1:0> fclk n fclk p lclk p lclk n dxx<1:0> fclk n fclk p lclk p lclk n dxx<1:0> fclk n fclk p lclk p lclk n dxx<1:0> phase_ddr<1:0>='00' (270 deg) phase_ddr<1:0>='10' (90 deg) phase_ddr<1:0>='01' (180 deg) phase_ddr<1:0>='11' (0 deg) figure 10 : lvds output timing adjustment d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 n n n n n n n n n n n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 input clock lclk p lclk n fclk p fclk n dxxx d0 d1 d2 d3 d4 d5 d6 d7 d8 n n n n n n n n n n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 fclk p fclk n dxxx d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n n n n n n n n n n n n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 fclk p fclk n dxxx lvds_delay = '1': lvds_advance = '1': default: t lvds d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 t lvds t lvds t prop t prop t prop preliminary product specification lvds drive strength programmability name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address ilvds_lclk<2:0> lvds current drive programmability for lclkp and lclkn pins. 3.5 ma drive x x x 0x11 ilvds_frame<2:0> lvds current drive programmability for fclkp and fclkn pins. 3.5 ma drive x x x ilvds_dat<2:0> lvds current drive programmability for output data pins. 3.5 ma drive x x x the current delivered by the lvds output drivers can be configured as shown in table 19 . the default current is 3.5ma, which is what the lvds standard specifies. setting the ilvds_lclk<2:0> register controls the current drive strength of the lvds clock output on the lclkp and lclkn pins. setting the ilvds_frame<2:0> register controls the current drive strength of the frame clock output on the fclkp and fclkn pins. setting the ilvds_dat<2:0> register controls the current drive strength of the data outputs on the d[8:1]p and d[8:1]n pins. table 19 : lvds output drive strength for lclk, fclk and data ilvds_*<2:0> lvds drive strength 000 3.5 ma (default) 001 2.5 ma 010 1.5 ma (rsds) 011 0.5 ma 100 7.5 ma 101 6.5 ma 110 5.5 ma 111 4.5 ma lvds internal termination programmability name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address en_lvds_term enables internal termination for lvds buffers. termination disabled x 0x12 term_lclk<2:0> programmable termination for lclkn and lclkp buffers. termination disabled 1 x x x term_frame<2:0> programmable termination for fclkn and fclkp buffers. termination disabled 1 x x x term_dat<2:0> programmable termination for output data buffers. termination disabled 1 x x x the off-chip load on the lvds buffers may represent a characteristic impedance that is not perfectly matched with the pcb traces. this may result in reflections back to the lvds outputs and loss of signal integrity. this effect can be mitigated by enabling an internal termination between the positive and negative outputs of each lvds buffer. internal termination mode can be selected by setting the en_lvds_term bit to '1'. once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. table 20 shows how the internal termination of the lvds buffers are programmed. the values are typical values and can vary by up to 20% from device to device and across temperature. ASD5020 rev 2.0 , 2010.11.08 high speed mode page 24 of 34 preliminary product specification table 20 : lvds output internal termination for lclk, fclk and data term_*<2:0> lvds internal termination 000 termination disabled 001 260 ? 010 150 ? 011 94 ? 100 125 ? 101 80 ? 110 66 ? 111 55 ? ASD5020 rev 2.0 , 2010.11.08 high speed mode page 25 of 34 preliminary product specification power mode control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address sleep4_ch<4:1> channel-specific sleep mode for a quad channel setup. inactive x x x x 0x0f sleep2_ch<2:1> channel-specific sleep mode for a dual channel setup. inactive x x sleep1_ch1 channel-specific sleep mode for a single channel setup. inactive x sleep go to sleep-mode. inactive x pd go to power-down. inactive x pd_pin_cfg<1:0> configures the pd pin function. pd pin configured for power-down mode x x lvds_pd_mode controls lvds power down mode high z-mode x 0x52 the ASD5020 device has several modes for power management, from sleep modes with short start up time to full power down with extremely low power dissipation. there are two sleep modes, both with the lvds clocks (fclk, lclk) running, such that the synchronization with the receiver is maintained. the first is a light sleep mode ( sleep*_ch ) with short start up time, and the second a deep sleep mode ( sleep ) with the same start up time as full power down. setting sleep4_ch preliminary product specification programmable gain name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address cgain_cfg configures the coarse gain setting x-gain enabled x 0x33 fine_gain_en enable use of fine gain. disabled x cgain4_ch1 <3:0> programmable coarse gain channel 1 in a quad channel setup. 1x gain x x x x 0x2a cgain4_ch2 <3:0> programmable coarse gain channel 2 in a quad channel setup. 1x gain x x x x cgain4_ch3 <3:0> programmable coarse gain channel 3 in a quad channel setup. 1x gain x x x x cgain4_ch4 <3:0> programmable coarse gain channel 4 in a quad channel setup. 1x gain x x x x cgain2_ch1 <3:0> programmable coarse gain channel 1 in a dual channel setup. 1x gain x x x x 0x2b cgain2_ch2 <3:0> programmable coarse gain channel 2 in a dual channel setup. 1x gain x x x x cgain1_ch1 <3:0> programmable coarse gain channel 1 in a single channel setup. 1x gain x x x x fgain_branch1<6:0> programmable fine gain for branch1. 1x / 0db gain x x x x x x x 0x34 fgain_branch2<6:0> programmable fine gain for branch 2. 1x / 0db gain x x x x x x x fgain_branch3<6:0> programmable fine gain for branch 3. 1x / 0db gain x x x x x x x 0x35 fgain_branch4<6:0> programmable fine gain for branch 4. 1x / 0db gain x x x x x x x fgain_branch5<6:0> programmable fine gain for branch 5. 1x / 0db gain x x x x x x x 0x36 fgain_branch6<6:0> programmable fine gain for branch 6. 1x / 0db gain x x x x x x x fgain_branch7<6:0> programmable fine gain for branch 7. 1x / 0db gain x x x x x x x 0x37 fgain_branch8<6:0> programmable fine gain for branch 8. 1x / 0db gain x x x x x x x the device includes a digital programmable gain in addition to the full-scale control. the programmable gain of each channel can be individually set using a four bit code, indicated as cgain*<3:0> . the gain is configured by the register cgain_cfg , when cgain_cfg equals '0' a gain in db steps is enabled as defined in table 21 otherwise if cgain_cfg equals '1' the gain is defined by table 22 . table 21 : gain setting C db step cgain_cfg cgain*<3:0> implemented gain [db] 0 0000 0 0 0001 1 0 0010 2 0 0011 3 0 0100 4 0 0101 5 0 0110 6 0 0111 7 0 1000 8 0 1001 9 0 1010 10 0 1011 11 0 1100 12 0 1101 not used 0 1110 not used 0 1111 not used ASD5020 rev 2.0 , 2010.11.08 high speed mode page 27 of 34 preliminary product specification table 22 : gain setting - x step cgain_cfg cgain*<3:0> implemented gain factor [x] 1 0000 1 1 0001 1.25 1 0010 2 1 0011 2.5 1 0100 4 1 0101 5 1 0110 8 1 0111 10 1 1000 12.5 1 1001 16 1 1010 20 1 1011 25 1 1100 32 1 1101 50 1 1110 not used 1 1111 not used there is a digital fine gain implemented for each adc branch to adjust the fine gain errors between the branches. the gain is controlled by fgain_branch* as defined in table 23 . for the high speed interleaved modes, there will be no missing codes when using digital fine gain, due to higher resolution internally (1 bit). the relationship between channels and adc branches is shown in tables 24 - 26 . to enable the fine gain function the register bit fine_gain_en has to be activated, set to '1'. table 23 : fine gain setting fgain_branchx<6:0> arithmetic function implemented gain (x) gain (db) 0 1 1 1 1 1 1 out=(1+ 2 -8 +2 -9 +2 -10 + 2 -11 +2 -12 +2 -13 )*in 1.0077 0.0665 0 1 1 1 1 1 0 out=(1+ 2 -8 +2 -9 +2 -10 + 2 -11 +2 -12 )*in 1.0076 0.0655 0 1 1 1 1 0 1 out=(1+ 2 -8 +2 -9 +2 -10 + 2 -11 +2 -1 3 )*in 1.0074 0.0644 0 1 1 1 1 0 0 out=(1+ 2 -8 +2 -9 +2 -10 + 2 -11 )*in 1.0073 0.0634 0 0 0 0 0 1 1 out=(1 + 2 -12 + 2 -1 3 )*in 1.0004 0.0031 0 0 0 0 0 1 0 out=(1 + 2 -12 )*in 1.0002 0.0021 0 0 0 0 0 0 1 out=(1 + 2 -1 3 )*in 1.0001 0.0010 0 0 0 0 0 0 0 out=in 1.0000 0.0000 1 1 1 1 1 1 1 out= in 1.0000 0.0000 1 1 1 1 1 1 0 out=(1- 2 -13 )*in 0.9999 -0.0011 1 1 1 1 1 0 1 out=(1 - 2 -12 )*in 0.9998 -0.0021 1 1 1 1 1 0 0 out=(1 - 2 -12 - 2 -1 3 )*in 0.9996 -0.0032 1 0 0 0 0 1 1 out=(1- 2 -8 -2 -9 -2 -10 - 2 -11 )*in 0.9927 -0.0639 1 0 0 0 0 1 0 out=(1- 2 -8 -2 -9 -2 -10 - 2 -11 -2 -1 3 )*in 0.9926 -0.0649 1 0 0 0 0 0 1 out=(1- 2 -8 -2 -9 -2 -10 - 2 -11 -2 -12 )*in 0.9924 -0.0660 1 0 0 0 0 0 0 out=(1- 2 -8 -2 -9 -2 -10 - 2 -11 -2 -12 - 2 -13 )*in 0.9923 -0.0670 ASD5020 rev 2.0 , 2010.11.08 high speed mode page 28 of 34 preliminary product specification analog input invert name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address invert4_ch<4:1> channel specific swapping of the analog input signal for a quad channel setup. ipx is positive input x x x x 0x24 invert2_ch<2:1> channel specific swapping of the analog input signal for a dual channel setup. ipx is positive input x x invert1_ch1 channel specific swapping of the analog input signal for a single channel setup. ipx is positive input x the ipx pin represents the positive analog input pin, and inx represents the negative (complementary) input. setting the bits marked invertx_ch preliminary product specification theory of operation ASD5020 is a multi mode high-speed, cmos adc, consisting of 8 adc branches, configured in different channel modes, using interleaving to achieve high speed sampling. for all practical purposes, the device can be considered to contain 4 adcs. fine gain is adjusted for each of the eight branches separately. ASD5020 utilizes a lvds output, described in 'register description, lvds output configuration and control'. the clocks needed (fclk, lclk) for the lvds interface are generated by an internal pll. the ASD5020 operate from one clock input, which can be differential or single ended. the sampling clocks for each of the four channels are generated from the clock input using a carefully matched clock buffer tree. internal clock dividers are utilized to control the clock for each adc during interleaving. the clock tree is controlled by the mode of operations. ASD5020 uses internally generated references. the differential reference value is 1v. this results in a differential input of ?1v to correspond to the zero code of the adc, and a differential input of +1v to correspond to the maximum code. the adc employs a pipeline converter architecture. each pipeline stage feeds its output data into the digital error correction logic, ensuring excellent differential linearity and no missing codes. ASD5020 operates from two sets of supplies and grounds. the analog supply and ground set is identified as avdd and avss, while the digital set is identified by dvdd and dvss. interleaving effects and sampling order interleaving adcs will generate interleaving artifacts caused by gain, offset and timing mismatch between the adc branches. the design of ASD5020 has been optimized to minimize these effects. it is not possible, though, to eliminate mismatch completely, such that additional compensation may be needed. the internal digital fine gain control may be used to compensate for gain errors between the adc branches. due to the optimization of ASD5020 there is not a one-to-one correspondence between the sampling order, lvds output order and the branch number. tables 24 , 25 and 26 give an overview of the corresponding branches, lvds outputs and sampling order for the different high speed modes. table 24 : quad channel mode channel # sampling order lvds output fine gain branch 1 1 d1a 1 2 d1b 2 2 1 d2a 3 2 d2b 4 3 1 d3a 5 2 d3b 6 4 1 d4a 7 2 d4b 8 table 25 : dual channel mode channel # sampling order lvds output fine gain branch 1 1 d1a 1 2 d1b 3 3 d2a 2 4 d2b 4 2 1 d3a 5 2 d3b 7 3 d4a 6 4 d4b 8 table 26 : single channel mode channel # sampling order lvds output fine gain branch 1 1 d1a 1 2 d1b 6 3 d2a 2 4 d2b 5 5 d3a 8 6 d3b 3 7 d4a 7 8 d4b 4 recommended usage analog input the analog input to ASD5020 is a switched capacitor track-and-hold amplifier optimized for differential operation. operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. the vcm pin provides a voltage suitable as common mode voltage reference. the internal buffer for the vcm voltage can be switched off, and driving capabilities can be changed programming the ext_vcm_bc<1:0> register. figure 12 shows a simplified drawing of the input network. the signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22 ohm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip ASD5020 rev 2.0 , 2010.11.08 high speed mode page 30 of 34 figure 12 : input configuration track track track track hold hold inx ipx preliminary product specification side of the resistors may be used to provide dynamic charging currents and may improve performance. the resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. dc-coupling figure 13 shows a recommended configuration for dc- coupling. note that the common mode input voltage must be controlled according to specified values. preferably, the cm_ext output should be used as reference to set the common mode voltage. figure 13 : dc coupled input the input amplifier could be inside a companion chip or it could be a dedicated amplifier. several suitable single ended to differential driver amplifiers exist in the market. the system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with ASD5020 input specifications. detailed configuration and usage instructions must be found in the documentation of the selected driver, and the values given in figure 13 must be adjusted according to the recommendations for the driver. ac-coupling figure 14 : transformer coupled input a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 14 shows a recommended configuration using a transformer. make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. the bandwidth should preferably exceed the sampling rate of the adc several times. it is also important to minimize phase mismatch between the differential adc inputs for good hd2 performance. this type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. magnetic coupling between the transformers and pcb traces may impact channel crosstalk, and must hence be taken into account during pcb layout. if the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the adc input. this could reduce the adc performance. to avoid this effect, the source must effectively terminate the adc kick-backs, or the traveling distance should be very short. figure 15 shows ac-coupling using capacitors. resistors from the cm_ext output, r cm , should be used to bias the differential input signals to the correct voltage. the series capacitor, c i , form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. note that start up time from sleep mode and power down mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. clock input and jitter considerations typically high-speed adcs use both clock edges to generate internal timing signals. in ASD5020 only the rising edge of the clock is used. the input clock can be supplied in a variety of formats. the clock pins are ac-coupled internally, hence a wide common mode voltage range is accepted. differential clock sources such as lvds, lvpecl or differential sine wave can be connected directly to the input pins. for cmos inputs, the clkn pin should be connected to ground, and the cmos clock signal should be connected to clkp. for differential sine wave clock input the amplitude must be at least +/- 0.8 vpp. no additional configuration is needed to set up the clock source format. the quality of the input clock is extremely important for high-speed, high-resolution adcs. the contribution to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1 . snr jitter = 20 ? log 2 ? ? f in ? t ( 1 ) where f in is the signal frequency, and t is the total rms jitter measured in seconds. the rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. this can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to ASD5020 rev 2.0 , 2010.11.08 high speed mode page 31 of 34 ipx inx cm_ext input input amplifier 43 43 33 pf figure 15 : ac coupled input ipx inx cm_ext 22 22 22 pf c i c i r cm r cm innx inpx ipx inx cm_ext input 33 33 r t 47 preliminary product specification all circuitry in the clock distribution. it is of utmost importance to avoid crosstalk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. the jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter performance is obtained with lvds or lvpecl clock with fast edges. cmos and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be re- timed with a low jitter master clock as the last operation before it is applied to the adc clock input. application usage example this section gives an overview on how ASD5020 can be used in an application utilizing all active modes with a single clock source. the example assumes that a low jitter 500mhz clock source is applied. a differential clock should be used, and can be generated from a single ended low jitter crystal oscillator, using a transformer or balun in conjunction with ac-coupling to convert from single ended to differential signal. start-up initialization the start-up sequence will be as follows: ? apply power ? apply reset (resetn low, then high, or spi command 0x00 0x0001) ? set power down (pd pin high or spi command 0x0f 0x0200) ? set lvds bit clock phase (phase_ddr, register 0x42)) if other than default must be used (depends on the receiver). ? select operating mode, for instance dual channel mode, and clock divider factor 2 (spi command 0x31 0x0102). ? set active mode (pd pin low or spi command 0x0f 0x0000) ? select analog inputs, for instance input 1 on channel 1 and input 3 on channel 2 (spi commands 0x3a 0202 and 0x3b 0808) change mode when changing operational mode, power down must be activated due to internal synchronization routines. a typical mode change will then be like this: ? set power down (pd pin high or spi command 0x0f 0x0200) ? change mode to for example single channel mode, and set the clock divider factor to 1 (spi command 0x31 0x0001) ? set active mode (pd pin low or spi command 0x0f 0x0000) ? select analog inputs, for instance input 1 (spi commands 0x3a 0202 and 0x3b 0202) table 27 gives an overview of the operational modes in this example and the spi commands to apply for each mode. table 27 : overview of operating modes and setup conditions operating mode sampling speed [msps] clock divider factor spi command for mode selection and clock divider single channel 500 1 0x31 0x0001 dual channel 250 2 0x31 0x0102 quad channel 125 4 0x31 0x0204 select analog input when an operational mode is selected, the analog inputs can be changed 'on-the-fly'. to change analog input one merely have to apply the dedicated spi commands. the change will occur instantaneously at the end of each spi command. table 28 : example of some analog input selections operating mode signal input selection spi commands single channel ip4/in4 0x3a 1010, 0x3b 1010 dual channel ch1: ip2/in2 ch2: ip3/in3 0x3a 0404, 0x3b 0808 quad channel ch1: ip4/in4 ch2: ip3/in3 ch3: ip2/in2 ch4: ip1/in1 0x3a 1008, 0x3b 0402 quad channel ch1: ip1/in1 ch2: ip2/in2 ch3: ip3/in3 ch4: ip4/in4 0x3a 0204, 0x3b 0810 ASD5020 rev 2.0 , 2010.11.08 high speed mode page 32 of 34 preliminary product specification package mechanical data qfn48 table 29 : qfn48 dimensions millimeter inch symbol min typ max min typ max a 0.8 0.9 1.0 0.031 0.035 0.039 a1 0.00 0.02 0.05 0.000 0.0008 0.002 a2 0.2 0.008 b 0.18 0.25 0.3 0.007 0.010 0.012 d 7.00 bsc 0.276 bsc d2 5.15 5.3 5.4 0.203 0.209 0.213 l 0.3 0.4 0.5 0.012 0.016 0.020 e 0.50 bsc 0.020 bsc f 0.6 0.024 ASD5020 rev 2.0 , 2010.11.08 high speed mode page 33 of 34 e f a2 b d d2 d 1 d d 2 a pin 1 id radius 0.3 a1 l pin 0, exposed pad bottom view pin 1 id (top side) 1 48 12 13 24 25 36 37 preliminary product specification product information product status datasheet revision date ASD5020 preliminary product specification 2.0 2010.11.08 ordering information model temp. range package type package drawing msl, peak temp (1) transport media ASD5020 l640int -40 to +85 c 48 pin qfn qfn48 level 2a tray (1) msl, peak temp: the moisture sensitivity level rating classified according to the jedec industry standard and to peak solder temperature. datasheet status objective product specification: the values and functionality describe design targets only. specifications and functionality can be changed without notice preliminary product specification: the specifications are based on initial design results. specifications and functionality can be changed without notice. product specification: information is current as of publication data. products conform to specifications according to the terms of arctic silicon devices as standard warranty. production does not necessarily require all parameters to be tested. arctic silicon devices as vestre rosten 81 n-7075 tiller norway tel: +47 73 10 29 00 fax: +47 73 10 29 19 information provided in this document is believed to be accurate and reliable. however, no responsibility is assumed by arctic silicon devices as for its use. neither is any responsibility assumed for any infringement of patents or other third party rights that may result from the use of the product or information described herein. no license is implicitly or otherwise granted under any patent or patent right of arctic silicon devices as. arctic silicon devices as specifically disclaims any and all liability, including without limitation incidental or consequential damages. it is the responsibility of the user to ensure that in all respects the application in which arctic silicon devices as products are used is suited to the purpose of the end user. life support applications : products of arctic silicon devices as (asd) are not designed for use in life support appliances, devices or systems, where malfunction can result in personal injury. customers using or selling asd products for use in such applications do so at their own risk and agree to fully indemnify asd for any damages resulting from such improper use or sale. all rights reserved ?. reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. ASD5020 rev 2.0 , 2010.11.08 high speed mode page 34 of 34 template rev. date: 2009.06.12 |
Price & Availability of ASD5020
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |